Reduction of power consumption is demanded in LSIs (Large Scale Integrated circuits) used in various fields. Power consumption due to parasitic capacitance of wirings is an element of power consumption in the LSI. A power consumption W due to a parasitic capacitance of a wiring is calculated using the following equation, for example.W=1/2×a×f×C×V×V 
Here, “a” represents an operation rate (activity) of a signal, “f” represents an operating frequency, “C” represents a parasitic capacitance of a wiring, and “V” represents a voltage.
The operation rate of a signal “a” is also called a toggle rate of a signal or an inversion rate of a signal value. Power consumption can be reduced by improving a wiring design of the LSI so as to reduce parasitic capacitances of wirings. However, power consumption values of respective wirings are not displayed in the conventional LSI layout designing CAD (Computer Aided Design) tool. Therefore, it is difficult to determine a wiring in which parasitic capacitance may be reduced to improve the wiring design of the LSI, and improvement of the wiring design depends on the skill of a designer.
The foregoing equation for calculating the power consumption of the LSI includes a term that is the product of the parasitic capacitance and the operation rate. The parasitic capacitance, which is correlated with a wiring area, can be estimated by the conventional LSI layout designing CAD tool. However, the operation rate cannot be estimated by the conventional LSI layout designing CAD tool.
The conventional LSI layout designing CAD tool has a disadvantage in that it is difficult for a designer to analyze wirings of an LSI and change the design thereof.    [Patent Document 1] Japanese Laid-open Patent Publication No. 07-106424    [Patent Document 2] Japanese Laid-open Patent Publication No. 2005-182632